High density electronic packages often referred to as multi-chip modules (MCM) or so-called systems in a package (SiP) have been designed and fabricated to satisfy the increasing demand for high levels of functionality in small packages. Products that may be combined within the these electronic packages include memory, digital logic, analog and digital processing devices, and analog Radio Frequency (RF) circuits, passives, sensors, FPGA, MEMS, etc. Typical integration of high density electronic devices achieves a density that is many times greater than, for example, surface mount technology (SMT).
Conventional fabrication techniques for these high density electronic devices include, for example, forming electronic modules such as integrated circuits, Through Substrate Vias (TSVs), and the like, positioning the electronic components on a mounting surface, encapsulating the resulting arrayed electronic modules in a mold material, forming one or more electrical layers along surfaces of the mold material (e.g., top-side electrical layers, bottom-side electrical layers, etc.) to yield a resultant reconstituted wafer fabrication based module. Typically, depending on the application, multiple wafer fabrication based modules are stacked together to form more complex electronic components according to application requirements, with the stacking done at either wafer or at individual module level. However, per module, the underlying chip density remains limited by relative placement and orientation of the contained electronic devices within the modules relative to a single 2D mounting surface. Accordingly, a need remains for devices and fabrication techniques that improve space utilization via 3D integration for each wafer based multi-chip module.